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NXP Semiconductors /MIMXRT1011 /OCOTP /HW_OCOTP_CTRL_SET

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Interpret as HW_OCOTP_CTRL_SET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDR0 (BUSY)BUSY 0 (ERROR)ERROR 0 (RELOAD_SHADOWS)RELOAD_SHADOWS 0WR_UNLOCK

Description

OTP Controller Control Register

Fields

ADDR

OTP write and read access address register
BUSY

OTP controller status bit
ERROR

Set by the controller when an access to a locked region(OTP or shadow register) is requested
RELOAD_SHADOWS

Set to force re-loading the shadow registers (HW/SW capability and LOCK)
WR_UNLOCK

Write 0x3E77 to enable OTP write accesses

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data